The level (e.g., voltage level or resistance level) of a memory cell may drift over time. Such drift will eventually corrupt the value stored in the memory cell. Multi-level cells (MLCs) that store multiple bits per cell are particularly sensitive to drift, although single-level cells (SLCs) that store a single bit per cell may also suffer from drift. While error-correction coding (ECC) may be used to repair bit errors resulting from drift in memory cells, the use of ECC to detect and correct such errors reduces performance. Accordingly, there is a need for techniques to mitigate memory cell drift.